Write data transfers for DRAM memory systems generally involve transmitting serialized streams of data from a memory controller to one or more DRAM devices. At the device, the serial streams are deserialized and fed to a memory core for storage in address-specified locations. Low-power DRAMs, such as LPDDR (and its variants), omit and employ various features that impact the timing of write data transfer operations.
For example, low-power DRAMs typically omit the use of an on-chip delay-locked-loop (DLL) for timing synchronization. The memory device's timing reference is thus obtained from an off-chip system clock or command clock. Further, low power DRAMs generally provide the ability to transfer data at one of several possible data rates. For relatively low data rates, write data is accompanied by a strobe timing reference having a preamble component that is set to a relatively short interval width. Faster data rates often use a strobe having a preamble with a longer length in order to meet timing constraints. Complicating matters further, the data strobe and system clock signals are referenced to the same clock domain, but traverse different paths on and off chip. While the data is referenced to the strobe signal, the command input and various control signals on the DRAM are referenced to the system clock or command clock. The two clocks can vary with respect to each other by up to a quarter clock cycle. This may pose problems in maintaining proper timing accuracy for write operations at the various data rates.
Thus, the need exists for an improved DRAM timing scheme for memory write operations that can minimize power dissipation while maximizing timing accuracy.